An Efficient Area Utilization of FM0, Manchester and Miller Encoding Architecture for DSRC Applications

Originally the DSRC applications requires encoding techniques for secure communication which include FM0 and Manchester encoding architecture. On analysis and observing the FM0 and Manchester encoding together in an initial hardware architecture. An effective utilization is more which leads to substantial area consumption. Hence, we adopt SOLS technique which merges architecture together and synchronize the operation. The circuit obtained is an integrated architecture of FM0, Manchester and Miller encoding to overcoming various drawbacks of traditional method. This deduced architecture of FM0 and Manchester coding would well support the DSRC standards. The performance of this paper is evaluated on Xilinx FPGA Spartan-3E kit. This paper not only develops a fully reused VLSI architecture, but also exhibits an effective performance compared with existing works.